The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A peripheral component interconnect express (PCIe) bridge interconnects a host system to peripheral devices. The PCIe bridge transfers data between the host system and the peripheral devices via an interface bus (e.g., an advanced extensible interface (AXI) bμs). The peripheral devices can include Ethernet devices, universal serial bus (USB) devices, serial advanced technology attachment (SATA) devices, and/or wireless local area network (WLAN) devices. The PCIe bridge may also transfer data between the host system and PCIe-bus-master capable modules such as interrupt controllers and embedded central processing units (CPUs). A first-in-first-out (FIFO) buffer can be connected between the PCIe bridge and the interface bus. Interconnection of the host system, the peripheral devices and the PCIe-bus-master capable modules can be realized via the interface bus. As an example, each of the peripheral devices may initiate data transfer requests to the host system via the FIFO buffer, the interface bus and the PCIe bridge. Data including user data, data transfer requests and control information can be transferred between the peripheral devices and a memory in the host system.
A PCIe bridge can operate in an active state (or state L0) and in a low power state (or state L1). The PCIe bridge including a physical layer (PHY) device and a controller of the PCIe bridge is fully powered during the active state. During the low power state, one or more PCIe components of the PCIe bridge can be powered down and/or clock gating to the PCIe components may be stopped. Clock gating refers to supplying a clock signal to one or more components.
Data is transferred during the active state of the PCIe bridge. If no data is being transferred, the PCIe bridge can transition from the active state to the low power state to reduce power consumption. A period during which the PCIe bridge transitions from the active state to the low power state is referred to as an entry latency period tenter. A period during which the PCIe bridge transitions from the low power state to the active state is referred to as an exit latency period texit. For a typical PCIe bridge, the entry latency period can be 2 micro-seconds (μs) in length and the exit latency period can be 16 μs in length.
Data transfer bandwidth of a PCI bridge is based on several parameters. The parameters include data width of a bus, frequency of a bus, and number of parallel PCIe lanes. A PCIe bridge is typically designed to realize a maximum data throughput under worst case conditions. In other words, bandwidth utilization for data transfers can be nearly 100%. However, bandwidth utilization of a PCIe bridge is typically less than 100%.